40 Gbps demonstrated in newly developed chipset at 140 GHz
On October 22nd, researchers from Chalmers University of Technology and Ericsson Research presented an attention-grabbing record of 40 Gbps bitrate for a single carrier chipset in the 140 GHz band. The work was presented in the breaking news session at the Compound Semiconductor Integrated Circuits Symposium conference (CSICS) in San Diego, California.
The rise of the mobile broadband has triggered a demand for increased bandwidth and spectrum for mobile services. In the coming years we will see an increased commercial use of radio access services on microwave and mm-wave frequencies. As a consequence, fixed wireless broadband services will be pushed towards higher frequency bands in order to find spectrum to be able to cope with the capacity needs.
Today, the highest frequency band in commercial use is the 70-80 GHz band. One motivation behind the work presented at CSICS is to push the “spectrum frontier” further beyond 100 GHz, where large chunks of currently unused spectra are available. A second aim is to develop hardware for wireless data communication with the possibility to support bitrates above 100 Gigabit per second. Key technologies to reach these goals are newly developed integrated circuit processes in Silicon and Indium Phosphide (InP). The first chipset with fairly high level of integration was newly designed, fabricated, and tested. It is based on a bipolar transistor process from Teledyne Scientific. The D-band (110-170 GHz) chipset is designed for a center frequency of 140 GHz. In order to demonstrate the huge bandwidth of this technology, a record high bitrate of 40 Gbps was achieved with direct I-Q modulation, using Quadrature Phase Shift Keying (QPSK). This is twice as fast as the previous world record at a comparable frequency. As a result of the record, the researchers was asked to present their results under the heading "Breaking News" at the Compound Semiconductor Integrated Circuits Symposium conference in San Diego.
Figure 1: This photo shows the 140 GHz transmitter chip, containing an I-Q modulator, a 3-stage amplifier, and a x3 frequency multiplier for the local oscillator. The chip was designed by Sona Carpenter, Herbert Zirath, and Mingquan Bao. Data-transmission measurements was done by Simon He. The chip size is 1.6x1.2 mm2.
At the conference, the research team from Chalmers will also present a 320 GHz receiver chip in the same InP technology, with an integrated antenna, sub-harmonic mixer, and an IF buffer amplifier, suitable for beam-steering and multi pixel imaging arrays.
The project has been funded by SSF, The Swedish Foundation for Strategic Research and the Swedish research Council (VR).
Herbert Zirath, Ericsson Research and Chalmers
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