Make the most out of last level cache in Intel Processors

Research paper

In modern (Intel) processors, Last Level Cache (LLC) is divided into multiple slices and an undocumented hashing algorithm (aka Complex Addressing) maps different parts of memory address space among these slices to increase the effective memory bandwidth. After a careful study of Intel’s Complex Addressing, we introduce a sliceaware memory management scheme, wherein frequently used data can be accessed faster via the LLC.


Amir Roozbeh, Ericsson Research. Alireza Farshin, Gerald Q. Maguire Jr, Dejan Kostić, KTH Royal Institute of Technology.

Accepted to EuroSys 2019, March 25-28, Dresden, Germany.